Low power consumption is an important requirement in the design of data processing systems. For example many applications such as cell phones, personal digital assistants, and the like are powered by a battery. In order to avoid frequent battery changes or the need to connect the battery to a charger, it is desirable that all integrated circuits consume a minimum amount of power. Modern digital integrated circuit fabrication techniques use complementary metal oxide semiconductor (CMOS) transistors that facilitate low power consumption. CMOS logic circuits only consume significant amounts of power when they are switching and integrated circuits built using CMOS technology, or significant portions thereof, may be designed to operate statically, allowing the power to be reduced during periods of inactivity.
Early power reduction techniques were hardware based. For example in an electronic hand held calculator, the user would enable the arithmetic circuitry by depressing a key. The arithmetic circuitry would input the operands and perform the calculation before shutting down.
However these techniques proved to be inadequate for microprocessors which might, for example, perform periodic functions independent of any user input. U.S. Pat. No. 4,758,945 invented by James J. Remedi discloses two software-based techniques for power reduction. The first technique, known as WAIT mode, causes the clock signals to be interrupted between the oscillator and the data processing system in response to a WAIT instruction. WAIT mode takes advantage of the fact that clock signals provided to a static CMOS microprocessor can be interrupted without the microprocessor losing its state. The second technique is known as STOP mode. In STOP mode, not only are the microprocessor's clock signals interrupted, but the oscillator itself is also disabled. Thus even the power consumed by the oscillator circuit is saved. However exit from STOP mode requires a wake-up delay for the clock signals from the oscillator to stabilize before being driven to the microprocessor and STOP mode cannot be used in situations that require fast response to external events. In either WAIT mode or STOP mode, it is possible to continue to supply clock signals to an internal timer, known as a watchdog timer, to periodically wake up the microprocessor.
In MOS integrated circuits that have been placed in STOP mode, the only power consumed is due to leakage currents. In many battery-powered applications it is desirable to reduce power consumption further by eliminating even these leakage currents. However if operational power were removed from the chip, the watchdog timer would be unable to periodically reawaken the chip, and an external wakeup mechanism would be required. Furthermore such external wakeup mechanism requires additional components and adds to system cost. Thus there is a need for a new mode capable of reducing power consumption even further without increasing system cost.